1. Field of the Invention
The present invention generally relates to a read/write circuit used for a magnetic disk apparatus, or an optical disk apparatus. More specifically, the present invention is directed to a data separator and a signal processing circuit suitable for constructing a highly integrated circuit with a lower power consumption.
2. Description of the Related Art
In the conventional product, model No. WD1OC22, furnished from Western Digital Inc., since the data separator is formed entirely of CMOS devices (Complementary Metal Oxide Semiconductors), only a data separator capable of operating up to approximately 10 Mbps is available. The reason for the limitation in the data separation will be discussed later. In particular, such a limitation is caused by the operating speed the CMOS. Therefore, it is practically impossible to construct a data separator capable of being operated higher than 15 Mbps.
Also, another conventional data separator and (2-7) encoder/decoder circuit such as 32D532 of SSI Inc. are completely constructed of bipolar transistors. As a result, the power consumption of these circuits becomes approximately 1 W, so that the product reliability will be deteriorated if such a higher power consumption circuit is sealed within a package having a small surface.
Now, consideration will be given to a window generating Circuit functioning as a synchronization circuit employed in the data separator. The window generating circuit functions as a portion of a disk drive system as shown in FIG. 22A. The data read from a disk 1 is amplified by a read/write circuit 3, and thereafter converted into a corresponding pulse signal in a waveform shaping circuit 4. This pulse signal corresponds to an original read signal (RAW RD) 16 as illustrated in FIG. 22B. A phase sync circuit 12 employed in the data separator synchronizes RAW RD 16 with a VCO clock (VCOCLK) 15. Then, a window is generated in a circuit 90 so as to detect a pulse of the original read signal 16. By utilizing this window, a synchronization read signal (SRD) 17 is produced. In the circuit of FIG. 22A, reference numeral 10 indicates an encoder/decoder for converting the data, reference numeral 11 represents a disk controller, and reference numeral 2 denotes a spindle motor. Further, reference numeral 18 indicates a synchronization clock (SCLK) corresponding to the window and reference numeral 19 indicates a write signal.
However, the original read signal 16 contains a jitter component shown in FIG. 22B which is caused by various noises of the signal reproduction and also produced in the read/write circuit 3 and waveform shaping circuit 4, and the fluctuations in the disk rotation. In a normal condition, the jitter value becomes .+-.40% if the window width is selected to be .+-.50% from the center.
A jitter component generation mechanism will now be described. As shown in FIG. 22B, during the waveform reproduction step from the disk 1, the practical head reproduction waveform is equal to a synthesized waveform of the head reproduction waveform for a single reverse magnetization. As a consequence, when the reverse magnetization interval is short, magnetic interference is caused. Thus, peaks of the head reproduction waveform before and after the magnetic interference are shifted, as shown in FIG. 22B, as compared with the ideal head reproduction waveform of the single reverse magnetization. RAW RD 16 detects the actual peak of the head reproduction waveform and then forms it as a pulse signal. Accordingly, the front edge of RAW RD 16 is shifted. In general, since the data recorded on the disk 1 is random data, such a peak shift phenomenon frequently occurs.
The phase synchronization circuit 12 in the data separator, on the other hand, does not follow such a high-speed variation as a peak shift. As a result, when the window for detecting the pulse of the original read signal 16 is generated in the window generating circuit 90, a high precision synchronization circuit is required so as to position the read signal at the center of the window.
However, if the window generating circuit 90 functioning as the synchronization (referred to as a "sync") circuit is formed of CMOS gates, a precision window center alignment cannot be achieved. As previously described, since the normal read signal derived from the hard disk fluctuates more than .+-.40% of the window, the reproduction of the read signal cannot be performed if the window center alignment does not achieve .+-.8%. As previously stated, the deviation of the window centering in the former case becomes .+-.20%, which cannot satisfy the normal demand value .+-.8%. This is because a great influence is caused by the gate delay due to the wiring load if the length of the layout wiring becomes long in case of CMOS gates, and also as there is a large difference between the operating frequencies of two signals within the window generating circuit, a difference is induced between the local heating phenomena, which causes variations in the gate delay of the CMOS gates.
In the latter case of the previous conventional data separator, it is constructed entirely of bipolar arrangements, so that although a highly precision window aligment can be realized due to the window generating circuit formed by the bipolar gates, the power consumption becomes high. Since no care is taken to achieve the lower power consumption, a heavy load is applied on the power supply of the system.
Moreover, to adjust the above-described window center, an employment of a delay line with a tap has been proposed in, for instance, Japanese Laid-open Patent Application No. 59-167813 entitled "a phase sync circuit". That is, it is so designed that the original read signal is input via the delay line having a tap to the window generating circuit, and also an adjusting circuit for adjusting a delay amount in the delay line is employed. Thus, a check is made whether or not an error occurs by inputting the data which has been delayed by a predetermined delay amount, whereby a phase shift between the data pulse sequence and window is measured and this measured phase shift amount is adjusted to a proper value. However, according to this prior art, since data delayed by a predetermined delay amount is required, a higher precision is necessarily required in the delay line with a tap. Furthermore, no consideration is given to the temperature drift and aging effect of the delay line having a tap. This causes a problem in cost and precision.